Semiconductor package including a dummy pattern

ABSTRACT

A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2021-0093246 filed on Jul. 16,2021 in the Korean Intellectual Property Office, the disclosure of whichis incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor package, andmore particularly, to a semiconductor package including a dummy pattern.

DISCUSSION OF RELATED ART

A semiconductor package is a casing containing one or discretesemiconductor device or integrated circuits. A semiconductor package istypically configured such that a semiconductor chip may be mounted on aprinted circuit board (PCB) and bonding wires or bumps may be used toelectrically connect the semiconductor chip to the printed circuitboard. The PCB is used to connect the semiconductor package to theexternal environment via leads such as lands, balls or pins. As theelectronics industry continues to develop, many studies have beenconducted to increase reliability and durability of semiconductorpackages.

SUMMARY

Example embodiments of the present inventive concept provide asemiconductor package with increased reliability.

According to an example embodiment of the present inventive concept, asemiconductor package includes: a first substrate and a semiconductordevice on the first substrate, wherein the first substrate includes: afirst dielectric layer including a first hole; a second dielectric layeron the first dielectric layer and including a second hole that overlapsthe first hole, the second hole being wider than the first hole; anunder bump disposed in the first hole and the second hole, the underbump covering a portion of the second dielectric layer; and a connectionmember bonded to the under bump.

According to an example embodiment of the present inventive concept, asemiconductor package includes: a package substrate; an interposersubstrate on the package substrate; a first semiconductor device and asecond semiconductor device mounted side by side on the interposersubstrate; and a thermal radiation member that covers the firstsemiconductor device, the second semiconductor device, the interposersubstrate, and the package substrate, wherein the interposer substrateincludes: a first dielectric layer including a first hole; a seconddielectric layer disposed on the first dielectric layer and including asecond hole that overlaps the first hole, the second hole being widerthan the first hole; an under bump disposed in the first hole and thesecond hole, the under bump covering a portion of the second dielectriclayer; a connection member bonded to the under bump; and a dummy patternspaced apart from the under bump, the dummy pattern penetrating thesecond dielectric layer and contacting the first dielectric layer,wherein a portion of the dummy pattern covers a top surface of thesecond dielectric layer, wherein a bottom surface of the dummy patternis coplanar with a bottom surface of the second dielectric layer, andwherein an interval between the under bump and the dummy pattern isabout 5 μm to about 50 μm.

According to an example embodiment of the present inventive concept, asemiconductor package includes: a first substrate and a semiconductordevice on the first substrate, wherein the first substrate includes: afirst dielectric layer; an under bump and a dummy pattern that are inthe first dielectric layer and are spaced apart from each other; and aconnection member in contact with a bottom surface of the under bump,wherein each of the under bump and the dummy pattern includes: a firstpart inserted into the first dielectric layer; and a second part thatprotrudes beyond the first dielectric layer and covers a top surface ofthe first dielectric layer, wherein a sidewall of the first part of theunder bump has an inflection point, and wherein a bottom surface of thedummy pattern is covered with a portion of the first dielectric layer.

According to an example embodiment of the present inventive concept, asemiconductor package includes: a first substrate and a semiconductordevice on the first substrate, wherein the first substrate includes: afirst dielectric layer; and an under bump and a dummy pattern that arein the first dielectric layer and are spaced apart from each other,wherein each of the under bump and the dummy pattern includes: a firstpart inserted into the first dielectric layer; and a second part thatprotrudes beyond the first dielectric layer and covers a top surface ofthe first dielectric layer, wherein the under bump has a firstthickness, and wherein the dummy pattern has a second thickness lessthan the first thickness.

According to an example embodiment of the present inventive concept, asemiconductor package includes: a first substrate and a semiconductordevice on the first substrate, wherein the first substrate includes: afirst dielectric layer that includes a first hole; an under bump thatincludes a first part and a second part, the first part disposed in thefirst hole, and the second part covering a top surface of the firstdielectric layer; and a connection member bonded to the under bump,wherein the under bump includes: a barrier/seed pattern that covers aninner sidewall of the first hole; and a bump metal pattern disposed onthe barrier/seed pattern and filling the first hole, wherein theconnection member is in contact with the bump metal pattern and isspaced apart from the barrier/seed pattern.

According to an example embodiment of the present inventive concept, asemiconductor package includes: a first substrate and a semiconductordevice on the first substrate, wherein the first substrate includes: afirst dielectric layer; first, second, and third under bumps that are inthe first dielectric layer and are spaced apart from each other, thefirst, second and third under bumps having the same shape; a first dummypattern between the first under bump and the second under bump; and asecond dummy pattern between the second under bump and the third underbump, wherein, when viewed in plan, a shape of the first dummy patternis different from a shape of the second dummy pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a plan view showing a semiconductor package accordingto some example embodiments of the present inventive concept.

FIG. 2A illustrates a cross-sectional view taken along line A-A′ of FIG.1 .

FIG. 2B illustrates a cross-sectional view taken along line B-B′ of FIG.1 .

FIG. 3A illustrates an enlarged view showing section P1 of FIG. 1 .

FIG. 3B illustrates a cross-sectional view showing an under bump anddummy patterns according to some example embodiments of the presentinventive concept.

FIG. 3C illustrates an enlarged view showing section P2 of FIG. 2A.

FIGS. 4A and 4B illustrate enlarged views showing section P3 of FIG. 3C.

FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H and 5I illustrate enlargedcross-sectional views showing a method of fabricating a semiconductorpackage having the enlarged cross-section of FIG. 3C according to someexample embodiments of the present inventive concept.

FIG. 6 illustrates a cross-sectional view taken along line A-A′ of FIG.1 .

FIG. 7 illustrates a plan view showing a semiconductor package accordingto some example embodiments of the present inventive concept.

FIG. 8 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcept.

FIG. 9 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcept.

FIG. 10 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Some example embodiments of the present inventive concept will now bedescribed in detail with reference to the accompanying drawings. In thisdescription, such terms as “first” and “second” may be used todistinguish identical or similar components from each other, and thesequence of such terms may be changed in accordance with the order ofmention.

FIG. 1 illustrates a plan view showing a semiconductor package accordingto some example embodiments of the present inventive concept. FIG. 2Aillustrates a cross-sectional view taken along line A-A′ of FIG. 1 .FIG. 2B illustrates a cross-sectional view taken along line B-B′ of FIG.1 . FIG. 3A illustrates an enlarged view showing section P1 of FIG. 1 .FIG. 3B illustrates a cross-sectional view showing an under bump anddummy patterns according to some example embodiments of the presentinventive concept. FIG. 3C illustrates an enlarged view showing sectionP2 of FIG. 2A. FIGS. 4A and 4B illustrate enlarged views showing sectionP3 of FIG. 3C.

FIGS. 1, 2A, 2B, and 3A to 3C, a semiconductor package 1000 according tothe present embodiment may be configured such that a semiconductordevice CH may be mounted on a first redistribution substrate RD1. Thesemiconductor device CH and the first redistribution substrate RD1 maybe covered with a mold layer MD.

The first redistribution substrate RD1 may include first, second, third,fourth, fifth, sixth and seventh dielectric layers IL1, IL2, IL3, IL4,IL5, IL6 and IL7 that are sequentially stacked. The first redistributionsubstrate RD1 may further include an under bump UB, dummy patterns DU1and DU2, first, second, third and fourth redistribution patterns RP1,RP2, RP3 and RP4, and a redistribution conductive pad RPA. The first toseventh dielectric layers IL1 to IL7 may each include, for example, aphoto-imageable dielectric (PID). The under bump UB, the dummy patternsDU1 and DU2, the first to fourth redistribution patterns RP1 to RP4, andthe redistribution conductive pad RPA may each include a conductivematerial.

For example, the first dielectric layer IL1 may be thinner than anyother of the first to seventh dielectric layers IL1 to IL7. As shown inFIG. 3B, the first dielectric layer IL1 may have a first thickness T1.The second dielectric layer IL2 may have a second thickness T2 greaterthan the first thickness T1. The first thickness T1 may be about ½ toabout 1/20 of the second thickness T2. The thicknesses of each of thethird to seventh dielectric layers IL3 to IL7 may be about ⅔ to about3/2 of the second thickness T2. The first dielectric layer IL1 may belocated at the bottom of the semiconductor package 1000.

The first redistribution substrate RD1 may include a plurality of underbumps UB that are two-dimensionally arranged along a first direction X1and a second direction X2. The under bumps UB may be provided on theredistribution substrate RD1 with external connection members OSB bondedthereto. The external connection members OSB may be, for example, solderballs, conductive bumps, or conductive pillars. The external connectionmembers OSB may include, for example, one or more of tin, nickel,silver, copper, gold, and aluminum. The dummy patterns DU1 and DU2 maybe disposed between the under bumps UB. A range of about 5 μm to about50 μm may be an interval DS between the under bump UB and one of thedummy patterns DU1 and DU2. The under bumps UB may be exposed betweenthe first dielectric layer IL1 for connecting with the externalconnection members OSB.

As shown in FIG. 3A, when viewed in plan, the under bump UB may have acircular shape with a third width W3. As illustrated in FIG. 3B, thefirst dielectric layer IL1 may include a first hole HL1 with a firstwidth W1. The second dielectric layer IL2 may have a second hole HL2that overlaps the first hole HL1 and has a second width W2 greater thanthe first width W1. The under bump UB may be inserted into the firsthole HL1 and the second hole HL2. The under bump UB may be exposed tothe outside via the first hole HL1.

The under bump UB may include a bump metal pattern 50 and a firstbarrier/seed pattern SP1. The first barrier/seed pattern SP1 may cover aportion of a top surface IL2_U of the second dielectric layer IL2, aninner sidewall of the second hole HL2, a portion of the first dielectriclayer IL1, and an inner sidewall of the first hole HL1.

The bump metal pattern 50 may include a first bump part 50 a insertedinto the first hole HL1, a second bump part 50 b inserted into thesecond hole HL2, and a third bump part 50 c that protrudes outwardlybeyond the top surface IL2_U of the second dielectric layer IL2. Thethird bump part 50 c may also be disposed on the top surface IL2_U ofthe second dielectric layer IL2. The first bump part 50 a may have abottom surface UB_B that is not covered with the first barrier/seedpattern SP1 and is in contact with the external connection member OSB.The first to third bump parts 50 a to 50 c may be integrally formed intoa single unitary piece. The first to third bump parts 50 a to 50 c mayeach have a circular shape when viewed in plan.

The first bump part 50 a may have the first width W1. The second bumppart 50 b may have the second width W2 greater than the first width W1.The third bump part 50 c may have the third width W3 greater than thesecond width W2. The under bump UB may have a T-shaped cross-section. Aportion of the third bump part 50 c may cover the top surface IL2_U ofthe second dielectric layer IL2. The second bump part 50 b maydownwardly protrude from a lower portion of the third bump part 50 c.The second bump part 50 b may fill the second hole HL2. The second bumppart 50 b may cover a portion of the top surface of the first dielectriclayer IL1. The first bump part 50 a may downwardly protrude from a lowerportion of the second bump part 50 b. The first bump part 50 a may fillthe first hole HL1.

Referring to FIG. 4A, the under bump UB may have a sidewall SW that hasan inflection point IFP adjacent to the top surface of the firstdielectric layer IL1. There are indistinct boundaries between the firstto seventh dielectric layers IL1 to IL7. For example, the firstdielectric layer IL1 and the second dielectric layer IL2 may have avague boundary therebetween, and may be considered as a singledielectric. In this case, the first hole HL1 and the second hole HL2 maybe merged together to form one bump hole. The inflection point IFP onthe sidewall SW of the under bump UB may be considered as an inflectionpoint on an inner sidewall of the bump hole.

The first barrier/seed pattern SP1 of the under bump UB may have abottom end in contact with the external connection member OSB.Alternatively, as shown in FIG. 4B, the first barrier/seed pattern SP1of the under bump UB may have a bottom end that is not in contact withthe external connection member OSB. Here, the first barrier/seed patternSP1 of the under bump UB is spaced apart from the external connectionmember OSB. Therefore, an air gap AG may be formed between the firstdielectric layer IL1 and the under bump UB. The air gap AG may bepositioned between the first barrier/seed pattern SP1 and the externalconnection member OSB.

As illustrated in FIG. 3A, the dummy patterns DU1 and DU2 may includefirst dummy patterns DU1 and second dummy patterns DU2 whose shape isdifferent from that of the first dummy patterns DU1. The first dummypatterns DU1 may be disposed in the first and second directions X1 andX2 between the under bumps UB. The under bumps UB may be providedbetween the second dummy patterns DU2 that are disposed in one of thirdand fourth directions X3 and X4. Each of the third and fourth directionsX3 and X4 is a diagonal direction that intersects both of the first andsecond directions X1 and X2.

In the present embodiment, when viewed in plan, the first dummy patternsDU1 may each have a circular shape with a fifth width W5. When viewed inplan, the second dummy patterns DU2 may each have a tetragonal shapewith concave sidewalls DSW2. The second dummy patterns DU2 may each havea seventh width W7 when viewed in plan.

The planar shapes of the first and second dummy patterns DU1 and UD2 maybe variously changed without being limited to that discussed above. Forexample, the first and second dummy patterns DU1 and DU2 mayindependently have a circular shape, an oval shape, a triangular shape,a tetragonal shape, a pentagonal shape, or any other shape. For anotherexample, the first and second dummy patterns DU1 and DU2 may have thesame shape and may have the same or different sizes.

Referring to FIG. 3B, the second dielectric layer IL2 may include afirst dummy hole DH1 and a second dummy hole DH2 that expose the topsurface of the first dielectric layer IL1. The first dummy pattern DU1may be disposed in the first dummy hole DH1 and may be in contact withthe top surface of the first dielectric layer IL1. The second dummypattern DU2 may be disposed in the second dummy hole DH2 and may be incontact with the top surface of the first dielectric layer IL1. Thefirst and second dummy patterns DU1 and DU2 may have respective bottomsurfaces DU1_B and DU2_B coplanar with a bottom surface IL2_B of thesecond dielectric layer IL2. The first and second dummy patterns DU1 andDU2 may each have a T-shaped cross-section.

The first dummy pattern DU1 may include a first dummy metal pattern 60and a second barrier/seed pattern SP2. The second barrier/seed patternSP2 may cover a portion of the top surface IL2_U of the seconddielectric layer IL2 and may also cover an inner sidewall and a bottomsurface of the first dummy hole DH1. The first dummy metal pattern 60may include a first dummy part 60 a inserted into the first dummy holeDH1 and a second dummy part 60 b that outwardly protrudes beyond the topsurface IL2_U of the second dielectric layer IL2. For example, thesecond dummy part 60 b may overlap the top surface IL2_U of the seconddielectric layer IL2. The first dummy part 60 a may have a bottomsurface that is covered with the second barrier/seed pattern SP2. Thesecond barrier/seed pattern SP2 may have a bottom surface that iscovered with the first dielectric layer IL1. The first dummy part 60 aand the second dummy part 60 b may be integrally formed into a singleunitary piece. The first dummy part 60 a and the second dummy part 60 bmay each have a circular shape when viewed in plan. The first dummy part60 a may have a fourth width W4. The second dummy part 60 b may have thefifth width W5 greater than the fourth width W4. A portion of the seconddummy part 60 b may cover the top surface IL2_U of the second dielectriclayer IL2. The first dummy part 60 a may downwardly protrude from alower portion of the second dummy part 60 b. In this case, the firstdummy part 60 a may fill the first dummy hole DH1.

The second dummy pattern DU2 may include a second dummy metal pattern 70and a third barrier/seed pattern SP3. The third barrier/seed pattern SP3may cover a portion of the top surface IL2_U of the second dielectriclayer IL2 and may also cover an inner sidewall and a bottom surface ofthe second dummy hole DH2. The second dummy metal pattern 70 may includea third dummy part 70 a inserted into the second dummy hole DH2 and afourth dummy part 70 b that outwardly protrudes beyond the top surfaceIL2_U of the second dielectric layer IL2. For example, the fourth dummypart 70 b may overlap the top surface IL2_U of the second dielectriclayer IL2. The third dummy part 70 a may have a bottom surface that iscovered with the third barrier/seed pattern SP3. The third barrier/seedpattern SP3 may have a bottom surface that is covered with the firstdielectric layer IL1. The third dummy part 70 a and the fourth dummypart 70 b may be integrally formed into a single unitary piece. Thethird dummy part 70 a and the fourth dummy part 70 b may each have atetragonal shape with concave sidewalls when viewed in plan.

The third dummy part 70 a may have a sixth width W6. The fourth dummypart 70 b may have the seventh width W7 greater than the sixth width W6.A portion of the fourth dummy part 70 b may cover the top surface IL2_Uof the second dielectric layer IL2. The third dummy part 70 a maydownwardly protrude from a lower portion of the fourth dummy part 70 b.In this case, the third dummy part 70 a may fill the second dummy holeDH2.

In the present embodiment, the third width W3 may range, for example,from about 100 μm to about 300 μm. The fifth width W5 may be less thanthe third width W3. The seventh width W7 may be greater than the fifthwidth W5. The seventh width W7 may be equal to or greater than the thirdwidth W3.

The under bump UB may have a top surface UB_U located at a first heightH1 from the top surface IL2_U of the second dielectric layer IL2. Thefirst dummy pattern DU1 may have a top surface DU1_U located at a secondheight H2 from the top surface IL2_U of the second dielectric layer IL2.The second dummy pattern DU2 may have a top surface DU2_U located at athird height H3 from the top surface IL2_U of the second dielectriclayer IL2. The first to third heights H1 to H3 may be equal to eachother. The first to third heights H1 to H3 may each range from about 5μm to about 20 μm. Alternatively, when the third width W3 and theseventh width W7 are equal to each other and greater than the fifthwidth W5 (W3=W7>W5), the first height H1 and the third height H3 may beequal to each other and may be less than the second height H2(H1=H3<H2).

The under bump UB may have a third thickness T3. The first dummy patternDU1 and the second dummy pattern DU2 may each have a fourth thicknessT4. The third thickness T3 may be greater than the fourth thickness T4.The second thickness T2 may be greater than the first height H1. Forexample, the fourth thickness T4 may be about 1.5 times to about 2.5times the first height H1. The fourth thickness T4 may range, forexample, from about 5 μm to about 20 μm.

Referring to FIG. 3C, a first angle θ1 may be made between the sidewallSW of the under bump UB and the bottom surface IL2_B of the seconddielectric layer IL2. A second angle θ2 may be made between a sidewallDSW_1 of the first dummy pattern DU1 and the bottom surface IL2_B of thesecond dielectric layer IL2. The first angle θ1 may be equal to thesecond angle θ2. The sidewall SW of the under bump UB may have a lengthgreater than that of the sidewall DSW1 of the first dummy pattern DU1.

The dummy patterns DU1 and DU2 may be supplied with no voltage and maybe electrically floated. Alternatively, at least one selected from thedummy patterns DU1 and DU2 may be provided with a ground voltage. Inthis case, at least one selected from the dummy patterns DU1 and DU2 maybe electrically connected to at least one selected from the first tofourth redistribution patterns RP1 to RP4.

The first, second, and third barrier/seed patterns SP1, SP2, and SP3 mayeach include, for example, a double structure of a seed layer includingcopper and a barrier layer including one selected from titanium,tantalum, titanium nitride, tantalum nitride, and tungsten nitride. Thebump metal pattern 50, the first dummy metal pattern 60, and the seconddummy metal pattern 70 may include the same first metal, for example,copper. The external connection members OSB may include, for example, asecond metal. The second metal may be, for example, at least oneselected from tin, silver, and nickel. The second metal may diffuse intothe bump metal pattern 50. For example, the second metal may be presentin the first bump part 50 a and the second bump part 50 b, but may beabsent in the third bump part 50 c.

The third dielectric layer IL3 may be disposed on the second dielectriclayer IL2. The third dielectric layer IL3 may cover the under bumps UBand the dummy patterns DU1 and DU2. In some example embodiments of thepresent inventive concept, since the under bumps UB and the dummypatterns DU1 and DU2 have T shapes, portions of the under bumps UB andthe dummy patterns DU1 and DU2 that protrude onto the second dielectriclayer IL2 may have a relatively small thickness. Therefore, there may bea reduction in step difference between the top surface IL2_U of thesecond dielectric layer IL2 and each of the top surfaces UB_U, DU1_U,and DU2_U of the under bumps UB and the dummy patterns DU1 and DU2, andthus, when the third dielectric layer IL3 is formed, it may be possibleto prevent an undulation of the third dielectric layer IL3 and to causethe third dielectric layer IL3 to have a flat top surface. Accordingly,process defects may be prevented to increase the reliability ofsemiconductor packages.

Moreover, in some example embodiments of the present inventive concept,because the dummy patterns DU1 and DU2 are disposed between the underbumps UB, when the third dielectric layer IL3 is formed, dishing orundulation issues may be reduced such that the third dielectric layerIL3 may have a flat top surface. Accordingly, process defects may beprevented to increase the reliability of semiconductor packages.

Furthermore, according to some example embodiments of the presentinventive concept, since the under bump UB has the inflection point IFPon the sidewall SW, the sidewall SW may become crooked and thus theunder bump UB may have a relatively large length on the sidewall SW.Therefore, the under bump UB and each of the first and second dielectriclayers IL1 and IL2 may have an increased contact area and thus have anincreased adhesive force. In addition, when the first barrier/seedpattern SP1 is etched to expose a bottom surface of the bump metalpattern 50 included in the under bump UB in fabrication process, whichwill be discussed with reference to FIGS. 5H and 5I, the firstbarrier/seed pattern SP1 may be prevented from being excessively etched.Accordingly, the occurrence of a crack or delamination may be preventedon a lateral surface of the under bump UB.

Referring to FIGS. 2A and 3C, the first redistribution patterns RP1 andthe first inner ground patterns IGP1 may be disposed on the thirddielectric layer IL3. The first inner ground patterns IGP1 may beconnected to each other to form a mesh shape when viewed in plan. Thefirst inner ground patterns IGP1 may be provided with a ground voltage.Portions of the first redistribution patterns RP1 may penetrate thethird dielectric layer IL3 and contact the under bumps UB. The firstinner ground patterns IGP1 may correspond to portions of the firstredistribution patterns RP1.

The fourth dielectric layer IL4 may cover the third dielectric layerIL3, the first redistribution patterns RP1, and the first inner groundpatterns IGP1. The second redistribution patterns RP2 may be disposed onthe fourth dielectric layer IL4. Portions of the second redistributionpatterns RP2 may penetrate the fourth dielectric layer IL4 and contactthe first redistribution patterns RP1. The fifth dielectric layer IL5may cover the fourth dielectric layer IL4 and the second redistributionpatterns RP2.

The third redistribution patterns RP3 and the second inner groundpatterns IGP2 may be disposed on the fifth dielectric layer IL5.Portions of the third redistribution patterns RP3 may penetrate thefifth dielectric layer IL5 and electrically connect with the secondredistribution patterns RP2. The second inner ground patterns IGP2 maybe connected to each other to form a mesh shape when viewed in plan. Thesecond inner ground patterns IGP2 may be provided with a ground voltage.The second inner ground patterns IGP2 may correspond to portions of thethird redistribution patterns RP3.

The sixth dielectric layer IL6 may cover the fifth dielectric layer IL5,the third redistribution patterns RP3, and the second inner groundpatterns IGP2. The fourth redistribution patterns RP4 may be disposed onthe sixth dielectric layer IL6. Portions of the fourth redistributionpatterns RP4 may penetrate the sixth dielectric layer IL6 andelectrically connect with the third redistribution patterns RP3. Theseventh dielectric layer IL7 may cover the sixth dielectric layer IL6and the fourth redistribution patterns RP4. The redistributionconductive pads RPA may be disposed on the seventh dielectric layer IL7.The redistribution conductive pads RPA may penetrate the seventhdielectric layer IL7 and electrically connect with the fourthredistribution patterns RP4.

One or more of the first to fourth redistribution patterns RP1 to RP4may be paths for electrical signals such as command/access signals.Another or more of the first to fourth redistribution patterns RP1 toRP4 may be paths for a ground voltage and/or a power voltage.

The first to fourth redistribution patterns RP1 to RP4, the first innerground patterns IGP1, the second inner ground patterns IGP2, and theredistribution conductive pads RPA may each include a fourthbarrier/seed pattern SP4 and a redistribution metal pattern IP, and atleast one of the redistribution metal patterns IP may include a via partVP that penetrates a corresponding one of the third to sixth dielectriclayers IL3 to IL6 and also include a line part LP disposed on the viapart VP. The via part VP and the line part LP may be integrally formedinto a single unitary piece. The fourth barrier/seed pattern SP4 mayinclude, for example, a double structure of a seed layer includingcopper and a barrier layer including one selected from titanium,tantalum, titanium nitride, tantalum nitride, and tungsten nitride. Theredistribution metal pattern IP may include, for example, copper.

The semiconductor device CH may be flip-chip mounted through innerconnection members ISB on the first redistribution substrate RD1. Thesemiconductor device CH may be one selected from an image sensor chipsuch as a complementary metal-oxide-semiconductor (CMOS) image sensor(CIS), a microelectromechanical system (MEMS) device chip, anapplication specific integrated circuit (ASIC) chip, and a memory devicechip such as a Flash memory chip, a dynamic random access memory (DRAM)chip, a static random access memory (SRAM) chip, an electricallyerasable programmable read only memory (EEPROM) chip, a phase changerandom access memory (PRAM) chip, a magnetic random access memory (MRAM)chip, a resistive random access memory (ReRAM) chip, a high bandwidthmemory (HBM) chip, and a hybrid memory cubic (HMC) chip. The innerconnection members ISB may be, for example, at least one selected fromsolder balls, conductive bumps, and conductive pillars. The innerconnection members ISB may include, for example, at least one selectedfrom tin, nickel, silver, copper, gold, and aluminum. The innerconnection members ISB may connect the redistribution conductive padsRPA to chip pads CPA of the semiconductor device CH.

An under fill layer UF may be interposed between the semiconductordevice CH and the first redistribution substrate RD1. The mold layer MDmay cover the semiconductor device CH and the first redistributionsubstrate RD1. The mold layer MD may include a dielectric resin, forexample, an epoxy molding compound (EMC). The mold layer MD may furtherinclude fillers, and the fillers may be dispersed in the dielectricresin. The fillers may include, for example, silicon oxide (SiO₂). Theunder fill layer UF may include a thermo-curable resin or aphoto-curable resin. In addition, the under fill layer UF may furtherinclude organic fillers or inorganic fillers.

FIGS. 5A to 5I illustrate enlarged cross-sectional views showing amethod of fabricating a semiconductor package having the enlargedcross-section of FIG. 3C according to some example embodiments of thepresent inventive concept.

Referring to FIGS. 2A and 5A, a sacrificial substrate SSB may beprepared. The sacrificial substrate SSB may be, for example, atransparent glass substrate or a bare wafer. A sacrificial layer REL maybe formed on the sacrificial substrate SSB. The sacrificial layer RELmay include an epoxy resin. The sacrificial layer REL may have, forexample, optical or thermal degradation properties. Alternatively, thesacrificial layer REL may include a conductive or dielectric materialhaving an etch selectivity with respect to a first dielectric layer IL1which will be discussed below. A first dielectric layer IL1 may beformed on the sacrificial layer REL. The first dielectric layer IL1 maybe formed by a coating process. The first dielectric layer IL1 may beformed of a photo-imageable dielectric (PID) layer. The first dielectriclayer IL1 may be formed to have the first thickness T1 of FIG. 3B.

Referring to FIGS. 2A and SB, the first dielectric layer IL1 may undergoexposure, development, and curing processes to form, in the firstdielectric layer IL1, first holes HL1 that expose the sacrificial layerREL. A second dielectric layer IL2 may be coated on the first dielectriclayer IL1 in which the first holes HL1 are formed. The second dielectriclayer IL2 may be formed to have the second thickness T2 of FIG. 3B. Aportion of the second dielectric layer IL2 may fill the first holes HL1.

Referring to FIGS. 2A, 3B, and 5C, the second dielectric layer IL2 mayundergo exposure, development, and curing processes to form second holesHL2, first dummy holes DH1, and second dummy holes DH2. The second holesHL2 may be formed to overlap the first holes HL1. The first dummy holesDH1 and the second dummy holes DH2 may be formed to expose a top surfaceof the first dielectric layer IL1. The second holes HL2 may be formed tohave their widths greater than those of the first holes HL1. Since thesecond dielectric layer IL2 is thicker than the first dielectric layerIL1, in the curing process, the second dielectric layer IL2 mayexperience shrinkage greater than that of the first dielectric layerIL1. Therefore, the second holes HL2 may partially expose a top surfaceof the first dielectric layer IL1. Since the second holes HL2, the firstdummy holes DH1, and the second dummy holes DH2 are simultaneouslyformed in the same exposure process, as discussed with reference to FIG.3C, the same angle (e.g., the first angle θ1 or the second angle θ2) maybe formed between the bottom surface IL2_B of the second dielectriclayer IL2 and the inner sidewalls of the second holes HL2, the firstdummy holes DH1, and the second dummy holes DH2.

Referring to FIGS. 2A, 3B, and 5D, a first barrier/seed layer SL1 may beconformally formed on entire surfaces (e.g., entire exposed surfaces) ofthe sacrificial substrate SSB, the first dielectric layer IL1, in whichthe first holes HL1 are formed, and the second dielectric layer IL2, inwhich the second holes HL2, the first dummy holes DH1, and the seconddummy holes DH2 are formed. First mask patterns MK1 may be formed on thefirst barrier/seed layer SL1. The first mask patterns MK1 may limitpositions of under bumps UB and dummy patterns DU1 and DU2 which will bediscussed below. The first mask patterns MK1 may be, for example,photoresist patterns. A plating process may be performed to form metalpatterns 50, 60, and 70 on the first barrier/seed layer SL1 exposed bythe first mask patterns MK1.

Referring to FIGS. 2A, 3B, and 5E, the first mask patterns MK1 may beremoved to expose the first barrier/seed layer SL1 on sides of the metalpatterns 50, 60, and 70. An etching process may be performed to removethe first barrier/seed layer SL1 on sides of the metal patterns 50, 60,and 70 and to form first, second, and third barrier/seed patterns SP1,SP2, and SP3. Therefore, there may be formed under bumps UB and dummypatterns DU1 and DU2. For example, the under bump UB may include themetal pattern 50 and the first barrier/seed pattern SP1, and the firstdummy pattern DU1 may include the metal pattern 60 and the secondbarrier/seed pattern SP2. A third dielectric layer IL3 may be coated onthe second dielectric layer IL2, the under bumps UB, and the dummypatterns DU1 and DU2. In this stage, the dummy patterns DU1 and DU2between the under bumps UB may increase flatness of the third dielectriclayer IL3. In addition, the under bumps UB and the dummy patterns DU1and DU2 may each have a T-shaped cross-section, and accordingly theflatness of the third dielectric layer IL3 may further increase.

Referring to FIGS. 2A, 5E, and 5F, the third dielectric layer IL3 mayundergo exposure, development, and curing processes to form, in thethird dielectric layer IL3, via holes VH that expose the under bumps UB.In this stage, since the flatness of the third dielectric layer IL3increases as described above, no failure may occur in the exposureprocess. Hence, the via hole VH may be precisely formed.

A second barrier/seed layer SL2 may be conformally formed on the thirddielectric layer IL3. Second mask patterns MK2 may be formed on thesecond barrier/seed layer SL2. The second mask patterns MK2 may limitpositions of first inner ground patterns IGP1 and first redistributionpatterns RP1 which will be discussed below. The second mask patterns MK2may include, for example, photoresist patterns. The second mask patternsMK2 may be formed by coating a photoresist layer and then exposing anddeveloping the photoresist layer. In this stage, since the flatness ofthe third dielectric layer IL3 increases as described above, no failuremay occur in the exposure process. Hence, the second mask patterns MK2may be precisely formed

A plating process may be performed to form a plating layer from a topsurface of the second barrier/seed layer SL2 that is exposed withoutbeing covered with the second mask patterns MK2, which may result in theformation of first inner ground patterns IGP1 and a redistribution metalpattern IP of first redistribution patterns RP1.

Referring to FIGS. 2A, 5F, and 5G, the second mask patterns MK2 may beremoved to expose the second barrier/seed layer SL2. The secondbarrier/seed layer SL2 may be removed which is exposed on sides of thefirst inner ground patterns IGP1 and the redistribution metal patternIP, and the fourth barrier/seed patterns SP4 may be formed below thefirst inner ground patterns IGP1 and the redistribution metal patternIP. The formation of the first inner ground patterns IGP1 and the firstredistribution patterns RP1 may be identically or similarly repeated toform fourth to seventh dielectric layers IL4 to IL7, second to fourthredistribution patterns RP2 to RP4, second inner ground patterns IGP2,and redistribution conductive pads RPA. Accordingly, a firstredistribution substrate RD1 may be manufactured.

Referring to FIGS. 2A and 5H, inner connection members ISB may be usedto bond a semiconductor device CH to the redistribution conductive padsRPA. An under fill layer UF may be formed between the semiconductordevice CH and the first redistribution substrate RD1.

Referring to FIGS. 2A, 5H, and 5I, the sacrificial layer REL and thesacrificial substrate SSB may be removed. In this case, when thesacrificial layer REL has optical degradation properties, light may beirradiated through the sacrificial substrate SSB. When the sacrificiallayer REL has thermal degradation properties, heat may be appliedadjacent to the sacrificial substrate SSB. Alternatively, thesacrificial substrate SSB may be physically separated from thesacrificial layer REL, and a remaining sacrificial layer REL may beremoved by an etching process or a chemical mechanical polishing (CMP)process. Therefore, there may be exposed a bottom surface of the firstdielectric layer IL1. In this stage, there may also be exposed a bottomsurface of the first barrier/seed pattern SP1 included in the under bumpUB. The exposed first barrier/seed pattern SP1 may undergo an etchingprocess to remove a portion of the first barrier/seed pattern SP1 and toexpose a bottom surface of a bump metal pattern 50 included in the underbump UB. A structure of FIG. 4A or 4B may be formed based on the degreeof etching of the first barrier/seed pattern SP1. In the presentembodiment, the first and second holes HL1 and HL2 may cause the firstbarrier/seed pattern SP1 to have an increased length. Thus, even if thefirst barrier/seed pattern SP1 is partially removed, a remaining firstbarrier/seed pattern SP1 may have a length sufficient enough to preventa crack or delamination on a sidewall of the under bump UB. Since thedummy patterns DU1 and DU2 are covered with the first dielectric layerIL1, the dummy patterns DU1 and DU2 may not be damaged in the etchingprocess.

Subsequently, referring to FIG. 3C, an external connection member OSBmay be bonded to the bottom surface of the bump metal pattern 50included in the under bump UB. In this stage, since the dummy patternsDU1 and DU2 are covered with the first dielectric layer IL1, electricalshorts may be prevented between the external connection member OSB andthe dummy patterns DU1 and DU2.

FIG. 6 illustrates a cross-sectional view taken along line A-A′ of FIG.1 .

Referring to FIG. 6 , a semiconductor package 1001 according to thepresent embodiment may be configured such that the dummy patterns DU1and DU2 may be provided with ground voltage. For example, one DUL1(G) ofthe first dummy patterns DU1 may be in contact with a via part of thefirst inner ground pattern IGP1. In addition, the first inner groundpattern IGP1 may be connected to the second inner ground pattern IGP2through one RP2(G) of the second redistribution patterns RP2. When thedummy patterns DU1 and DU2 are provided with a ground voltage asmentioned above, the dummy patterns DU1 and DU2 may serve as anelectromagnetic shield to reduce signal noise and to suppressinterference between electrical signals applied to adjacent under bumpsUB. Other configurations may be identical or similar to those discussedwith reference to FIGS. 1 to 4B.

FIG. 7 illustrates a plan view showing a semiconductor package accordingto some example embodiments of the present inventive concept. Across-section taken along line A-A′ of FIG. 7 may be identical orsimilar to that of FIG. 6 .

Referring to FIG. 7 , a semiconductor package 1002 according to thepresent embodiment may be configured such that when viewed in plan adummy pattern DU may have a mesh shape, in which the dummy patterns DU1and DU2 of FIG. 1 are connected to each other, and may surround theunder bumps UB. The dummy pattern DU may include a first dummy part 60 aand a second dummy part 60 b each of which constitutes a mesh shape. Thedummy pattern DU may be electrically floated or may be provided with aground voltage. When the dummy pattern DU is provided with a groundvoltage, the mesh shape of the dummy pattern DU may facilitateconnection of the first redistribution pattern RP1 or the first innerground pattern IGP1. Other configurations may be identical or similar tothose discussed with reference to FIGS. 1 to 4B.

FIG. 8 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcept.

Referring to FIG. 8 , a semiconductor package 1003 according to thepresent embodiment may have a package-on-package structure in which asecond sub-semiconductor package PKG2 is mounted on the firstsub-semiconductor package PKG1. The first sub-semiconductor package PKG1may include a first redistribution substrate RD1 and a firstsemiconductor device CH1 mounted on the first redistribution substrateRD1.

The first redistribution substrate RD1 may further include a signalpattern SGL for connection between the second sub-semiconductor packagePKG2 and the first semiconductor device CH1. The signal pattern SGL maybe a portion of the fourth redistribution patterns RP4. Otherconfigurations of the first redistribution substrate RD1 may beidentical or similar to those discussed with reference to FIGS. 1 to 4B.The first semiconductor device CH1 may be connected through a firstinner connection member ISB1 to a first redistribution conductive padRPA1 of the first redistribution substrate RD1. The first semiconductordevice CH1 and the first redistribution substrate RD1 may be coveredwith a first mold layer MD1 The first mold layer MD1 may have therein amold via MVA that penetrates therethrough. The mold via MVA may includeat least one metal selected from copper, aluminum, tungsten, nickel,gold, and tin.

A second redistribution substrate RD2 may be disposed on the first moldlayer MD1. The second redistribution substrate RD2 may include eighth,ninth and tenth dielectric layers IL8, IL9 and IL10 that aresequentially stacked, fifth and sixth redistribution patterns RP5 andRP6, and second redistribution conductive pads RPA2. The eighth to tenthdielectric layers IL8 to IL10 may each include a photo-imageabledielectric (PID). The fifth and sixth redistribution patterns RP5 andRP6 and the second redistribution conductive pads RPA2 may each includea conductive material.

The fifth redistribution pattern RP5 may be interposed between theeighth dielectric layer IL5 and the ninth dielectric layer IL9. Thefifth redistribution pattern RP5 may penetrate the eighth dielectriclayer IL8 and contact the mold via MVA. The sixth redistribution patternRP6 may be interposed between the ninth dielectric layer IL9 and thetenth dielectric layer IL10. The sixth redistribution pattern RP6 maypenetrate the ninth dielectric layer IL9 and contact the fifthredistribution pattern RP5. The second redistribution conductive padsRPA2 may be disposed on the tenth dielectric layer IL10, and maypenetrate the tenth dielectric layer IL10 and connect with the sixthredistribution pattern RP6.

Like the first to fourth redistribution patterns RP1 to RP4 discussedwith reference to FIGS. 1 to 4B, the fifth and sixth redistributionpatterns RP5 and RP6 may each include a fourth barrier/seed pattern SP4and a redistribution metal pattern IP. The first and secondredistribution conductive pads RPA1 and RPA2 may each be identical orsimilar to the redistribution conductive pad RPA discussed withreference to FIGS. 1 to 4B.

The second sub-semiconductor package PKG2 may include a firstsub-package substrate PS1, a second semiconductor device CH2 disposed onthe first sub-package substrate PS1, a first adhesion layer AD1interposed between the first sub-package substrate PS1 and the secondsemiconductor device CH2, a second mold layer MD2 that covers the firstsub-package substrate PS1 and the second semiconductor device CH2, andfirst wires WR1 that connect the first sub-package substrate PS1 to thesecond semiconductor device CH2. The first sub-package substrate PS1 maybe a double-sided or multi-layered printed circuit board. Alternatively,the first sub-package substrate PS1 may be another redistributionsubstrate.

The first and second semiconductor devices CH1 and CH2 may independentlybe one selected from an image sensor chip such as CMOS image sensor(CIS), a microelectromechanical system (MEMS) device chip, anapplication specific integrated circuit (ASIC) chip, and a memory devicechip such as a Flash memory chip, a dynamic random access memory (DRAM)chip, a static random access memory (SRAM) chip, an electricallyerasable programmable read only memory (EEPROM) chip, a phase changerandom access memory (PRAM) chip, a magnetic random access memory (MRAM)chip, a resistive random access memory (ReRAM) chip, a high bandwidthmemory (HBM) chip, and a hybrid memory cubic (HMC) chip.

Other configurations may be identical or similar to those discussed withreference to FIGS. 1 to 4B.

FIG. 9 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcept.

Referring to FIG. 9 , a semiconductor package 1004 according to thepresent embodiment may be configured such that the firstsub-semiconductor package PKG1 further may include a connectionsubstrate 900. The connection substrate 900 may be disposed on the firstredistribution substrate RD1. The connection substrate 900 may include acavity region CV into which the first semiconductor device CH1 isinserted. The connection substrate 900 may be connected through thirdinner connection members ISB3 to the first redistribution conductivepads RPA t of the first redistribution substrate RD1. A first under filllayer UF1 may be interposed between the first semiconductor device CH1and the first redistribution substrate RD1. A second under fill layerUF2 may be interposed between the connection substrate 900 and the firstredistribution substrate RD1.

The connection substrate 900 may include a plurality of base layers 910and a plurality of conductive structures 920. The base layers 910 areillustrated formed of two layers in the present embodiment, but thepresent inventive concept is not limited thereto, and the base layers910 may be formed of three or more layers. The base layers 910 mayinclude a dielectric material. For example, the base layers 910 mayinclude a carbon-based material, a ceramic, or a polymer.

The conductive structure 920 may include a connection pad 921, a firstconnection via 922, a first connection line 923, and a second connectionvia 924. In the present embodiment, the first connection via 922 and thefirst connection line 923 may be integrally formed into a single unitarypiece. The conductive structure 920 may include metal, such as copper,aluminum, gold, nickel, or titanium. The first mold layer MD1 may coverthe connection substrate 900.

The fifth redistribution pattern RP5 of the second redistributionsubstrate RD2 may penetrate the eighth dielectric layer IL8 and thefirst mold layer MD1, thereby being in contact with the secondconnection via 924. Other configurations may be identical or similar tothose discussed above with reference to FIG. 8 .

FIG. 10 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcept.

Referring to FIG. 10 , a semiconductor package 1005 according to thepresent embodiment may be configured such that the first redistributionsubstrate RD1 may be flip-chip mounted through fourth inner connectionmembers ISB4 on a first package substrate 100. The first packagesubstrate 100 may be, for example, a double-sided or multi-layeredprinted circuit board. Alternatively, the first package substrate 100may be another redistribution substrate. In the present embodiment, thefirst redistribution substrate RD1 may be called an interposersubstrate.

A plurality of external connection members OSB may be bonded to thefirst package substrate 100. The first sub-semiconductor package PKG1and the second sub-semiconductor package PKG2 may be mounted side byside on the first redistribution substrate RD1.

The first sub-semiconductor package PKG1 may include a first sub-packagesubstrate PS1, a first semiconductor device CH1 disposed on the firstsub-package substrate PS1, a first adhesion layer AD1 interposed betweenthe first sub-package substrate PS1 and the first semiconductor deviceCH1, a first mold layer MD1 that covers the first sub-package substratePS1 and the first semiconductor device CH1, and first wires WR1 thatconnect the first sub-package substrate PS1 to the first semiconductordevice CH1.

The second sub-semiconductor package PKG2 may include a secondsub-package substrate PS2, second semiconductor devices CH2 stacked onthe second sub-package substrate PS2, and a second mold layer MD2 thatcovers the second sub-package substrate PS2 and the second semiconductordevices CH2. At least one of the second semiconductor devices CH2 mayinclude one or more through vias TSV. The through via TSV may includemetal, such as copper or tungsten. The second semiconductor devices CH2may be electrically connected through second inner connection membersISB2 to the second sub-package substrate PS2. The second semiconductordevices CH2 may be, for example, memory chips. The second sub-packagesubstrate PS2 may be a logic chip that drives the memory chips.

The first sub-semiconductor package PKG1 may be connected through firstinner connection members ISB1 to the first redistribution substrate RD1.The second sub-semiconductor package PKG2 may be connected through thirdinner connection members ISB3 to the first redistribution substrate RD1.The first redistribution substrate RD1 may further include a signalpattern SGL that connects the first sub-semiconductor package PKG1 tothe second sub-semiconductor package PKG2. The signal pattern SGL may bea portion of the fourth redistribution patterns RP4. A thermal radiationmember HS may cover the first redistribution substrate RD1, the firstand second sub-semiconductor packages PKG1 and PKG2, and the firstpackage substrate 100.

A thermal interface material layer TIM may be interposed between thethermal radiation member HS and the first and second sub-semiconductorpackages PKG1 and PKG2. The thermal interface material layer TIM mayinclude a grease or thermosetting resin layer. The thermal interfacematerial layer TIM may further include filler particles dispersed in thethermosetting resin layer. The filler particles may include a graphenepowder or a metal powder whose thermal conductivity is high.Alternatively, the filler particles may include at least one selectedfrom silica, alumina, zinc oxide, and boron nitride.

A second adhesion layer AD2 may be interposed between the first packagesubstrate 100 and a bottom end of the thermal radiation member HS. Thefirst and second sub-semiconductor packages PKG1 and PKG2 may havetherebetween an empty space with no mold layer.

The thermal radiation member HS may include a material whose thermalconductivity is high, for example, graphene or metal such as tungsten,titanium, copper, or aluminum. The thermal radiation member HS mayinclude a conductive material. The thermal radiation member HS may alsoserve as an electromagnetic shield. Other configurations may beidentical or similar to those discussed with reference to FIGS. 1 to 4B.

A semiconductor package according to some example embodiments of thepresent inventive concept may be configured such that dummy patternsdisposed between under bumps may increase flatness of a dielectric layerlocated on the dummy patterns. In addition, the under bumps and thedummy patterns may each have T shapes to further increase the flatnessof the dielectric layer. Accordingly, process defects may be preventedto increase the reliability of the semiconductor package.

Moreover, since the under bump has an undulation on a sidewall thereof,an adhesive force between the under bump and the dielectric layer mayincrease to prevent a crack or delamination between the under bump andthe dielectric layer. As a result, the semiconductor package mayincrease in reliability.

Furthermore, the dummy pattern may be provided with a ground voltage andthus may serve as an electromagnetic shield.

Although the present inventive concept has been described in connectionwith some example embodiments thereof, it will be understood to thoseskilled in the art that various changes and modifications may be madethereto without departing from the technical spirit and scope of thepresent inventive concept. The embodiments of FIGS. 1 to 10 may becombined with each other.

1. A semiconductor package, comprising: a first substrate and asemiconductor device on the first substrate, wherein the first substrateincludes: a first dielectric layer including a first hole; a seconddielectric layer on the first dielectric layer and including a secondhole that overlaps the first hole, the second hole being wider than thefirst hole; an under bump disposed in the first hole and the secondhole, the under bump covering a portion of the second dielectric layer;and a connection member bonded to the under bump.
 2. The semiconductorpackage of claim 1, wherein a sidewall of the under bump has aninflection point.
 3. The semiconductor package of claim 1, wherein thefirst substrate further includes a dummy pattern spaced apart from theunder bump, the dummy pattern penetrating the second dielectric layerand contacting the first dielectric layer, wherein a portion of thedummy pattern covers a top surface of the second dielectric layer, andwherein a bottom surface of the dummy pattern is coplanar with a bottomsurface of the second dielectric layer.
 4. The semiconductor package ofclaim 3, wherein the dummy pattern is electrically floated or isprovided with a ground voltage.
 5. The semiconductor package of claim 3,wherein the dummy pattern and the under bump include the same metal, anda top surface of the dummy pattern is at the same as a top surface ofthe under bump.
 6. The semiconductor package of claim 3, wherein, whenviewed in plan, the dummy pattern has a circular shape, a tetragonalshape whose sidewalls are concave, or a mesh shape.
 7. The semiconductorpackage of claim 3, wherein the under bump has a first thickness, andthe dummy pattern has a second thickness less than the first thickness.8. The semiconductor package of claim 3, wherein an interval between theunder bump and the dummy pattern is about 5 μm to about 50 μm.
 9. Thesemiconductor package of claim 3, wherein the second dielectric layerincludes a dummy hole into which the dummy pattern is inserted, thedummy hole exposing a top surface of the first dielectric layer, whereinthe dummy pattern includes: a seed layer that covers an inner sidewalland a bottom surface of the dummy hole; and a dummy metal pattern thatfills the dummy hole.
 10. The semiconductor package of claim 9, whereinan inner sidewall of the second hole makes a first angle with a bottomsurface of the second dielectric layer, the inner sidewall of the dummyhole makes a second angle with the bottom surface of the seconddielectric layer, and the first angle is substantially the same as thesecond angle.
 11. The semiconductor package of claim 1, wherein theunder bump includes: a barrier/seed pattern that covers at least aninner sidewall of the second hole; and a bump metal pattern disposed onthe barrier/seed pattern and filling the second hole and the first hole,and wherein an air gap is provided between the bump metal pattern and aninner sidewall of the first hole.
 12. The semiconductor package of claim11, wherein the connection member is in contact with the bump metalpattern.
 13. A semiconductor package, comprising: a package substrate;an interposer substrate on the package substrate; a first semiconductordevice and a second semiconductor device mounted side by side on theinterposer substrate; and a thermal radiation member that covers thefirst semiconductor device, the second semiconductor device, theinterposer substrate, and the package substrate, wherein the interposersubstrate includes: a first dielectric layer including a first hole; asecond dielectric layer disposed on the first dielectric layer andincluding a second hole that overlaps the first hole, the second holebeing wider than the first hole; an under bump disposed in the firsthole and the second hole, the under bump covering a portion of thesecond dielectric layer; a connection member bonded to the under bump;and a dummy pattern spaced apart from the under bump, the dummy patternpenetrating the second dielectric layer and contacting the firstdielectric layer, wherein a portion of the dummy pattern covers a topsurface of the second dielectric layer, wherein a bottom surface of thedummy pattern is coplanar with a bottom surface of the second dielectriclayer, and wherein an interval between the under bump and the dummypattern is about 5 μm to about 50 μm.
 14. The semiconductor package ofclaim 13, wherein the dummy pattern is electrically floated or isprovided with a ground voltage.
 15. The semiconductor package of claim13, wherein the dummy pattern and the under bump include the same metal,and a top surface of the dummy pattern is at the same as a top surfaceof the under bump.
 16. The semiconductor package of claim 13, wherein,when viewed in plan, the dummy pattern has a circular shape, atetragonal shape whose sidewalls are concave, or a mesh shape.
 17. Asemiconductor package, comprising: a first substrate and a semiconductordevice on the first substrate, wherein the first substrate includes: afirst dielectric layer; an under bump and a dummy pattern that are inthe first dielectric layer and are spaced apart from each other; and aconnection member in contact with a bottom surface of the under bump,wherein each of the under bump and the dummy pattern includes: a firstpart inserted into the first dielectric layer; and a second part thatprotrudes beyond the first dielectric layer and covers a top surface ofthe first dielectric layer, wherein a sidewall of the first part of theunder bump has an inflection point, and wherein a bottom surface of thedummy pattern is covered with a portion of the first dielectric layer.18. The semiconductor package of claim 17, wherein a length of asidewall of the under bump is greater than a length of a sidewall of thedummy pattern.
 19. The semiconductor package of claim 17, wherein theunder bump includes: a barrier/seed pattern in contact with the firstdielectric layer; and a bump metal pattern on the barrier/seed patternand in contact with the connection member, wherein an air gap is betweenthe connection member and the barrier/seed pattern.
 20. Thesemiconductor package of claim 17, wherein, when viewed in plan, thedummy pattern has a circular shape, a tetragonal shape whose sidewallsare concave, or a mesh shape. 21.-30. (canceled)